The disclosure generally relates to an external network coprocessor and, more specifically, to techniques for connecting an external network coprocessor to a network processor packet parser.
High-performance network processors on a single chip may have to handle sophisticated network functions. For example, a packet parser in an Ethernet adapter may have to support high-level packet classification and packet filtering functions that cannot all be all handled on a network processor chip. In this case, a parser typically hands off some packet processing functions to an external coprocessor, which provides results that are used by the parser. In general, functions that are handed off from a parser may require different processing architectures and performance that a network processor chip is not able to include due to area limitation, as certain network functions may require logic and arrays that are relatively large.
A typical network processing function that may be externalized from a packet parser to a coprocessor is packet classification, which may include a lookup in a ternary content-addressable memory (TCAM) or a hash-based lookup for which different search algorithms are employed (e.g., a Patricia tree, a Cuckoo algorithm, etc.). Another function that can be externalized is packet filtering functions that are based on recognition of patterns extracted from a packet. In general, a packet parser connection to an external coprocessor should be flexible enough to adapt to various bandwidth requirements and to support external processor programmable technologies, e.g., field-programmable gate array (FPGA) technology, to facilitate various different final network processor system designs.
U.S. Pat. No. 7,428,618 (hereinafter “the '618 patent”) discloses a network node structure that is architected around two net processors (i.e., one net processor for each packet stream direction) that communicate via a shared memory (see, for example, FIG. 2). The structure includes a set of coprocessors located on a daughter card. The coprocessors are interconnected via hardware control logic that also provides an interface to one of the two net processors, via a dedicated memory. In the '618 patent, communication between coprocessors is facilitated by a dedicated interface for exchanging requests and responses between the coprocessors and the net processor via a dedicated memory.
U.S. Patent Application Publication No. 2003/0041172 (hereinafter “the '172 publication”) discloses a network node structure that allegedly improves performance, as compared to an existing network processor. According to the '172 publication, an external coprocessor is added to an existing network processor infrastructure. In general, the external coprocessor is not capable of running in a correlated way with the network processor, due to requirements for large buffers and complex state retrieval algorithms. Per the '172 publication, specific tasks are not executed in parallel with main packet handling by a network processor. In general, a physical interface to the coprocessor cannot be adjusted to various networking system requirements.